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automotive power data sheet rev. 1.0, 2010-02-18 TLE7236SE spi driver for enhanced relay control spider spi driver for enhanced relay control
data sheet 2 rev. 1.0, 2010-02-18 spi driver for enhanced relay control TLE7236SE table of contents table of contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.1 terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.1 pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.2 pin definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.2 functional range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.3 thermal resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5 power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.1 operation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.2 limp home mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.3 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.4 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6 power stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.1 input circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.2 channels 4 and 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.3 inductive output clamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6.4 timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.5 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.6 command description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 7 protection functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7.1 over load protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7.2 over temperature protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7.3 esd protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7.4 reverse polarity protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7.5 loss of v bb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7.6 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 8 diagnostic features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 8.1 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 8.2 command description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 9 serial peripheral interface (spi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 9.1 spi signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 9.2 daisy chain capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 9.3 spi protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 9.4 register overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 9.5 timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 9.6 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 10 package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 11 application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 12 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table of contents
pg-dso-20-45 type package marking TLE7236SE pg-dso-20-45 TLE7236SE data sheet 3 rev. 1.0, 2010-02-18 spi driver for enhanced relay control TLE7236SE TLE7236SE 1 overview features ? 8 bit spi for diagnostics and control, providing daisy chain capability ? very wide range for digital supply voltage ? two configurable input pins offer complete flexibility for pwm operation ? stable behavior at under voltage ? green product (rohs compliant) ?aec qualified description the TLE7236SE is an eight channel high-side and low-side power switch in pg-dso-20-45 package providing embedded protective functions. it is especially designed for standard relays and leds in automotive applications. the output stages incorporate two low-side, four high-side and two auto configuring high-side or low-side switches. a serial peripheral interface (spi) is utilized for control and diagnosis of the device and the load. for direct control, there are two input pins available. the TLE7236SE provides a micro controller fail-safe function which is activated via a high signal at the limp home input pin. there is a power supply integrated in the device to ensure this functionality even without digital supply voltage. the integrated power supply is designed to fulfill cranking mode requirements. the power transistors are built by n-channel power mosfets. the device is monolithically integrated in smart power technology.
data sheet 4 rev. 1.0, 2010-02-18 spi driver for enhanced relay control TLE7236SE overview protective functions ? over load and short circuit protection ? thermal shutdown ? electrostatic discharge protection (esd) diagnostic functions ? latched diagnostic information via spi ? open load detection in off-state ? over load detection in on-state ? over temperature crank mode ? integrated power supply enables secure operation at low battery voltage limp home / fail-safe functions ? limp home activation via pin lhi ? limp home configuration via input pins applications ? especially designed for driving relays and leds in automotive applications ? all types of resistive and inductive loads ? suitable to switch 5 v power supply lines by auto configuring channels table 1 product summary operating range power supply voltage v bb 4.0 ? 28 v digital supply voltage v dd 3.0 ? 5.5 v typical on-state resistance at 25 c r ds(on) high-side: 2 channels (relay) 0.85 ? high-side: 2 channels (generic, led) 1.6 ? auto configuring: 2 channels (relay, supplies) 0.85 ? low-side: 2 channels (relay) 0.85 ? nominal load current (all channels active) i l(nom, min) relay 280 ma led, generic 140 ma over load switch off threshold i ds(ovl, min) 500 ma output leakage current per channel at 25 c i ds(off, max) 1 a drain to source clamping voltage v ds(cl, min) 41 v source to ground clamping voltage v bb(cl, max) -40 v spi clock frequency f sclk(max) 5mhz
spi driver for enhanced relay control TLE7236SE overview data sheet 5 rev. 1.0, 2010-02-18 detailed description the TLE7236SE is an eight channel high-side and low-side relay switch providing embedded protective functions. the output stages incorporate two low-side switches (0.85 ? per channel), four high-side switches (two channels with 0.85 ? and two channels with 1.6 ? ) and two auto-configuring high-side or low-side switches (0.85 ? per channel). the auto-configuring switches can be utilized in high-side or low-side configuration just by connecting the load accordingly. they are also suitable to switch a 5 v supply line in high-side configuration. protective and diagnostic functions adjust automatically to the chosen configuration. the 8 bit serial peripheral interface (spi) is utilized for control and diagnosis of the device and the loads. the spi interface provides daisy chain capability in order to assemble multiple devices in one spi chain by using the same number of micro-controller pins. the outstanding feature of this octal relay switch enables the output channels to keep their state at low battery voltage. this is realized by an integrated power supply, especially designed to fulfill cranking mode requirements (v bat = 4 v) independent from digital power supply ( v dd ). the spi functionality is given only when the digital power supply is available. furthermore, the TLE7236SE is equipped with two input pins that can be individually routed to the output control of each channel thus offering complete flexibility in design and pcb-layout. the input multiplexer is controlled via spi. in limp home mode (fail-safe mode), the input pins are directly routed to the configurable output channels 4 and 5. the limp home mode operates independently of digital power supply and is activated via pin lhi. the device provides full diagnosis of the load via open load, over load and short circuit detection. spi diagnosis flags indicate latched fault conditions that may have occurred. each output stage is protected against short circuit. in case of over load, the affected channel switches off. there are temperature sensors available for each channel to protect the device against over temperature. the device protects itself with a built in reverse polarity protection which prohibits intrinsic current flow through the logic during reverse polarity. however the output stages still incorporate a reverse diode where current can flow through during reverse polarity. the power transistors are built by n-channel power mosfets. the inputs are ground referenced cmos compatible. the device is monolithically integrated in smart power technology.
data sheet 6 rev. 1.0, 2010-02-18 spi driver for enhanced relay control TLE7236SE block diagram 2 block diagram figure 1 block diagram overview_6.emf reverse polarity protection control, diagnostic and protective functions input mux out3 out2 in1 in2 limp home mode activation out1 out0 d4 d5 lhi crank mode power supply vbb gnd s4 s5 out7 out6 open load detection temperature sensor high-side gate control short circuit detection low-side gate control auto configuring gate control cs si sclk so diagnosis register input register vdd spi stand-by control
spi driver for enhanced relay control TLE7236SE block diagram data sheet 7 rev. 1.0, 2010-02-18 2.1 terms figure 2 shows all terms used in this data sheet. figure 2 terms in all tables of the electrical characteristics is valid: channel related symbols without channel number are valid for each channel separately (e.g. v ds specification is valid for v ds0 ? v ds7 ). in order to make the description of output currents easier, the load current i out is equivalent to the drain current i out_d in low-side configuration and the source current i out_s in high-side configuration. all spi register bits are marked as follows: addr.parameter (e.g. icr01.inx1) . in spi register description, the values in bold letters (e.g. 0 ) are default values. v cs v sc l k v si i so so i sc l k i si sclk si i cs cs v so gnd i gnd vbb i s vdd i dd in2 in1 i in 2 i in 1 v in 1 v dd v in 2 lhi i lhi v lhi terms_6.emf out0 out1 out2 out3 v bat v ds3 v ds1 v ds2 v ds0 v ds7 v ds6 d4 out6 out7 s5 v s5 v s4 v ds4 v s0 v s1 v s2 v s3 d5 s4 v ds5 v d5 v d4 i out_s1 i out_s3 i out_s0 i out_s2 i out_s5 i out_d7 i out_d4 i out_d6 i out_d5 i out_s4 TLE7236SE
data sheet 8 rev. 1.0, 2010-02-18 spi driver for enhanced relay control TLE7236SE pin configuration 3 pin configuration 3.1 pin assignment l figure 3 pin configuration pg-dso20-45 3.2 pin definitions and functions pin symbol i/o function power supply 18 vdd - digital power supply 1 vbb - power supply 10 gnd - digital, analog and power ground power stages 20 out0 o source of high side power transistor channel 0 2 out1 o source of high side power transistor channel 1 19 out2 o source of high side power transistor channel 2 3 out3 o source of high side power transistor channel 3 13 d4 o drain of auto configuring power transistor 4 11 s4 o source of auto configuring power transistor 4 7 d5 o drain of auto configuring power transistor 5 9 s5 o source of auto configuring power transistor 5 12 out6 o drain of low side power transistor channel 6 8 out7 o drain of low side power transistor channel 7 inputs 4 lhi i limp home activation input pin (pull down) (top view ) 2 3 4 5 6 7 8 9 out3 out1 out7 in1 in2 d5 s5 p-dso20-45.emf 10 gnd 1 vbb 19 18 17 16 15 14 13 12 vdd out2 d4 sclk si so out6 11 s4 20 out0 cs lhi
spi driver for enhanced relay control TLE7236SE pin configuration data sheet 9 rev. 1.0, 2010-02-18 5 in1 i input multiplexer input 1 pin (pull down) 6 in2 i input multiplexer input 2 pin (pull down) spi 17 cs i spi chip select (pull up) 16 sclk i serial clock 15 si i serial data in 14 so o serial data out pin symbol i/o function
data sheet 10 rev. 1.0, 2010-02-18 spi driver for enhanced relay control TLE7236SE electrical characteristics 4 electrical characteristics 4.1 absolute maximum ratings 1) stresses above the ones listed here may affect device reliability or may cause permanent damage to the device. the values below are not considering combinations of different maximum conditions at one time 1) not subject to production test t j = -40 c to +150 c; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) absolute maximum ratings 1) pos. parameter symbol limit values unit test conditions min. max. power supply 4.1.1 power supply voltage v bb -40 40 v -40v max. 2 minutes 4.1.2 digital supply voltage v dd -0.3 5.5 v ? 4.1.3 power supply voltage for short circuit protection (single pulse) v bat(sc) 028 v? power stages 4.1.4 load current i l a? channel 0, 1, 4, 5, 6, 7 -0.5 0.5 channel 2, 3 -0.25 0.25 4.1.5 voltage at power transistor v ds ?41 v? 4.1.6 power transistor?s source voltage v out_s -16 ? v ? 4.1.7 power transistor?s drain voltage v out_d ?41 v? 4.1.8 max. energy dissipation one channel single pulse for ch. 0, 1, 4, 5, 6, 7 e as mj 2) ?65 t j(0) = 105 c i d(0) = 0.35 a ?50 t j(0) = 150 c i d(0) = 0.250 a 4.1.9 maximum energy dissipation one channel repetitive pulses for ch. 0, 1, 4, 5, 6, 7 e ar mj 2) 110 4 cycles ? 18 t j(0) = 105 c i d(0) = 0.250 a 110 6 cycles ? 13 t j(0) = 105 c i d(0) = 0.220 a 4.1.10 max. energy dissipation one channel single pulse for ch. 2,3 e as mj 2) ?50 t j(0) = 105 c i d(0) = 0.250 a ?30 t j(0) = 150 c i d(0) = 0.250 a
spi driver for enhanced relay control TLE7236SE electrical characteristics data sheet 11 rev. 1.0, 2010-02-18 4.2 functional range note: within the functional range the ic operates as described in the circuit description. the electrical characteristics are specified within the conditions given in the related electrical characteristics table. 4.1.11 maximum energy dissipation one channel repetitive pulses for ch. 2,3 e ar mj 2) 110 4 cycles ? 12 t j(0) = 105 c i d(0) = 0.180 a 110 6 cycles ? 11 t j(0) = 105 c i d(0) = 0.180 a logic pins 4.1.12 voltage at input pins v in -0.3 v dd + 0.3 v 3) 4.1.13 voltage at lhi pin v lhi -0.3 5.5 v? 4.1.14 voltage at chip select pin v cs -0.3 v dd + 0.3 v 3) 4.1.15 voltage at serial clock pin v sclk -0.3 v dd + 0.3 v 3) 4.1.16 voltage at serial input pin v si -0.3 v dd + 0.3 v 3) 4.1.17 voltage at serial output pin v so -0.3 v dd + 0.3 v 3) temperatures 4.1.18 junction temperature t j -40 150 c? 4.1.19 storage temperature t stg -55 150 c? esd susceptibility 4.1.20 esd susceptibility on all pins v esd -2 2 kv hbm 4) 1) not subject to production test 2) pulse shape represents inductive switch off: i l ( t ) = i l (0) * (1 - t / t pulse ); 0 < t < t pulse 3) v dd + 0.3 v < 5.5 v 4) esd susceptibility, hbm according to eia/jesd 22-a114 pos. parameter symbol limit values unit conditions min. max. 4.2.1 supply voltage range for nominal operation v bb(nom) 916v? 4.2.2 upper supply voltage range for extended operation v bb(ext),up 16 28 v parameter deviations possible 4.2.3 lower supply voltage range for extended operation v bb(ext),low 4 9 v parameter deviations possible 4.2.4 junction temperature t j -40 150 c? t j = -40 c to +150 c; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) absolute maximum ratings 1) pos. parameter symbol limit values unit test conditions min. max.
data sheet 12 rev. 1.0, 2010-02-18 spi driver for enhanced relay control TLE7236SE electrical characteristics 4.3 thermal resistance note: this thermal data was generated in accordance with jedec jesd51 standards. for more information, go to www.jedec.org . thermal resistance 1) 1) not subject to production test pos. parameter symbol limit values unit conditions min. typ. max. 4.3.1 junction to case, bottom r thjc,back ??25k/w 2) 2) specified r thjsp value is simulated at natural convection on a cold plate setup (all pins are fixed to ambient temperature). t a = 85 c. ch1 to ch8 are dissipating 1 w power (0.125 w each). 4.3.2 junction to case, top r thjc,top ??30k/w 2) 4.3.3 junction to pin (5,6,15 or 16) r thjpin ??23k/w 2) 4.3.4 junction to ambient (1s0p, min. footprint) r thja,min ?80?k/w 3) 3) specified r thja value is according to jedec jesd51-2,-3 at natural convection on fr4 1s0p board; the product (chip+package) was simulated on a 76.2 x 114.3 x 1.5 mm board with minimal footprint copper area and 70 m thickness. t a = 85 c, ch1 to ch8 are dissipating 1 w power (0.125 w each). 4.3.5 junction to ambient (1s0p+300mm 2 cu) r thja,300 ?65?k/w 4) 4) specified r thja value is according to jedec jesd51-2,-3 at natural convection on fr4 1s0p board; the product (chip+package) was simulated on a 76.2 x 114.3 x 1.5 mm board with additional heatspreading copper area of 300mm 2 and 70 m thickness. t a = 85 c, ch1 to ch8 are dissipating 1 w power (0.125 w each). 4.3.6 junction to ambient (1s0p+600mm 2 cu) r thja,600 ?60?k/w 5) 5) specified r thja value is according to jedec jesd51-2,-3 at natural convection on fr4 1s0p board; the product (chip+package) was simulated on a 76.2 x 114.3 x 1.5 mm board with additional heatspreading copper area of 600mm 2 and 70 m thickness. t a = 85 c, ch1 to ch8 are dissipating 1 w power (0.125 w each). 4.3.7 junction to ambient (2s2p) r thja,2s2p ?52?k/w 6) 6) specified r thja value is according to jedec jesd51-2,-7 at natural convection on fr4 2s2p board; the product (chip+package) was simulated on a 76.2 x 114.3 x 1.5 mm board with 2 inner copper layers (2 x 70 m cu, 2 x 35 m cu). t a = 85 c, ch1 to ch8 are dissipating 1 w power (0.125 w each).
spi driver for enhanced relay control TLE7236SE power supply data sheet 13 rev. 1.0, 2010-02-18 5 power supply the TLE7236SE is supplied by two supply voltages v bb and v dd . the v bb supply line is connected to a battery feed and used by the power switches and by an integrated power supply for the register banks. the internal power supply is designed to hold the state of the power switches including the configuration stored in the control register bank during cranking down to 4v. there is an under voltage reset function implemented for the v bb power supply, which is triggered if v bb is below the undervoltage threshold. after start-up of the power supply, all spi registers are reset to their default values and the device is in sleep mode (standby). sending the spi command cmd.wake = 1 switches the device to operation mode (on), while a command cmd.stb = 1 send the device to sleep mode (standby) again. please note that the device needs the time t wu(sleep) to initialize itself. no spi command should be send after changing the power state via cmd.wake = 1 before this time is elapsed. a spi frame send during t wu(sleep) could be ignored. the v dd supply line is used to power the circuitry related to the spi shift register and for driving the so line. as a result, the daisy chain function is available as soon as v dd is provided in the specified range independent of v bb . a capacitor between pins v dd and gnd is recommended (especially in case of emi disturbances). please see figure 14 ?application diagram? on page 35 for details. 5.1 operation modes there is a limp home functionality implemented in the TLE7236SE, which is activated via pin lhi. please refer to section 5.2 for details. the device provides a sleep mode (stand by) to minimize current consumption, which also resets the register banks. it is entered and left by dedicated spi commands . the sleep mode current is minimized only when limp home is inactive. after limp home, the device enters sleep mode automatically. the internal power supply is designed for low voltage cranking condition down to v bb = 4 v. during cranking, the output channels keep their state as before configured via spi independent of v dd supply voltage. if v dd =0v the spi can not be used as the output and input levels refer to v dd , but the device keep the current state until either the limp home mode is triggered or the v dd voltages comes back and therefore the spi interface works again. the following table shows the operation modes depending on v bb , v dd and the limp home input signal lhi. 5.2 limp home mode the TLE7236SE offers the capability of driving dedicated channels during fail-safe operation of the system. this limp home mode is activated by a high signal at pin lhi. in limp home mode, the spi registers are reset and the input pins are directly routed to the auto configuring channels (channel 4 and 5). as a result, the limp home operation can be chosen for high-side and low-side driven loads. due to the integrated power supply, limp home operation is independent of digital power supply v dd . in case of stand-by, a high signal at pin lhi will wake up the device. after limp home operation, the device enters sleep mode in any case. operation modes vbb 0v0v0v4v4v4v12v12v12v12v vdd 0v5v5v0v0v3v0v0v5v5v lhi x 0v 5v 0v 4v 0v 0v 5v 0v 5v switches operating - - - ??????? limp home - - - - ? -- ? - ? spi & daisy-chain - ? ? -- ? -- ? ? register banks reset reset reset ? reset ? ? reset ? reset diagnostic functions ------ ? - ? -
data sheet 14 rev. 1.0, 2010-02-18 spi driver for enhanced relay control TLE7236SE power supply 5.3 reset there are several reset trigger implemented in the device. a reset switches off all channels and sets the registers to default values. after any kind of reset, the transmission error flag (ter) is set and the device is in sleep mode. under voltage reset: during this device condition a read on spi delivers the standard diagnostic frame with a ter flag, if v dd is above the under voltage threshold already, if not spi is not working. this under voltage reset is released when v dd and v bb supply voltage levels are above under voltage threshold. reset command: there is a reset command available to reset all register bits of the register bank and the diagnosis registers. as soon as cmd.rst = 1, a reset is triggered. limp home mode: in limp home mode, the spi write-registers are reset. the spi interface is operating normally, so the limp home bit lhi as well as the diagnosis flags can be read, but no command is accepted until the device leaves the limp home operation.
spi driver for enhanced relay control TLE7236SE power supply data sheet 15 rev. 1.0, 2010-02-18 5.4 electrical characteristics note: characteristics show the deviation of parameter at the given supply voltage and junction temperature. typical values show the typical parameters expected at v bb = 13.5 v, v dd = 5.0 v, t j = 25 c. unless otherwise specified: v dd = 3.0 v to 5.5v, v bat = 9.0 v to 16v, t j = -40 c to +150 c pos. parameter symbol limit values unit test conditions min. typ. max. power supply v bb 5.4.1 supply voltage range for nominal operation v bb(nom) 916v? 5.4.2 upper supply voltage range for extended operation v bb(ext),up 16 28 v parameter deviations possible 5.4.3 lower supply voltage range for extended operation v bb(ext),low 4 9 v r l = 80 ? v ds < 1.5 v parameter deviations possible 5.4.4 under voltage reset threshold v bb(uv) ?? 4v v dd = 0v 5.4.5 operating current drawn from v bb i s(on) ??15ma 1) v bb = 16 v ??12ma v bb = 16 v all diagnosis off 5.4.6 sleep mode operating current with disconnected loads (stand by) i s(sleep) ??10 a v bb = 16 v v lhi = 0 v ; awk = 0 t j = 25 c 1) 1) not subject to production test, specified by design. ??13 t j = 85 c 1) ??20 t j = 150 c digital power supply v dd 5.4.7 logic supply voltage v dd 3.0 ? 5.5 v 5.4.8 under voltage reset threshold v dd(po) ??3.0v 5.4.9 logic supply current i dd(on) ??0.4ma f sclk = 0 hz awk = 1 v cs = 0v 5.4.10 logic supply current during vbb dropout i dd(do) ?35ma 1) f sclk = 0 hz v bb < v bb(uv) awk = 1 v cs = 0v 5.4.11 logic supply sleep mode current i dd(sleep) ??20 a v cs = v dd awk = 0 t j = 25 c 1) ??20 t j = 85 c 1) ??40 t j = 150 c timings 5.4.12 sleep mode wake-up time t wu(sleep) ? ? 200 s 1) 5.4.13 v bb under voltage reset delay time t bb(uvr) ??1 s 1) 5.4.14 v dd under voltage reset delay time t dd(uvr) ??1 s 1)
data sheet 16 rev. 1.0, 2010-02-18 spi driver for enhanced relay control TLE7236SE power stages 6 power stages the TLE7236SE is an eight channel high-side and low-side relay switch. the power stages are built by n-channel vertical power mosfet transistors. the gates of the high-side switches are controlled by charge pumps. 6.1 input circuit there are two input pins available at TLE7236SE, which can be configured to be used for control of the output stages. the inxn parameter of the input configuration register provide following possibilities: ? channel is switched off ? channel is switched according to signal level at input pin in1 ? channel is switched according to signal level at input pin in2 ? channel is switched on figure 4 shows the input circuit of TLE7236SE. figure 4 input multiplexer the current sink to ground ensures that the channels switch off in case of open input pin. the zener diode protects the input circuit against esd pulses. 6.2 channels 4 and 5 the TLE7236SE provides two auto-configuring high-side or low-side switches (channels 4 and 5). they adjust the diagnostic and protective functions according their potentials at drain and source automatically. in high-side configuration, the load is connected between ground and source of the power transistors (s4 or s5). the drain of the power transistors (d4 and d5) can be connected to any potential between gnd-pin potential and vbb-pin potential. when the drain is connected to vbb, the channel behave like the other high side channels. the drain can also be connected to a 5 v power supply and the source pin will be utilized as switched 5 v supply line. in low-side configuration, the source of the power transistors are to be connected to gnd. the configuration can be chosen for each of these channels individually, so it is feasible to connect one channel in low-side and the other in high-side configuration. channel 7 channel 6 channel 5 channel 4 channel 3 channel 2 channel 1 in1 i in1 in2 i in2 channel 0 1 0 inx0 i nputlogic.emf
spi driver for enhanced relay control TLE7236SE power stages data sheet 17 rev. 1.0, 2010-02-18 6.3 inductive output clamp when switching off inductive loads with low-side switches, the potential at pin out rises to v ds(cl) potential, because the inductance intends to continue driving the current. for the high-side channels, the potential at pin out drops below ground potential to v s(cl) . the voltage clamping is necessary to prevent destruction of the device, see figure 5 for details. nevertheless, the maximum allowed load inductance is limited by the max. clamping energy e ar see electrical characteristics ? e ar ? on page 10 . figure 5 output clamp implementation maximum load inductance during demagnetization of inductive loads, energy has to be dissipated in the TLE7236SE. this energy can be calculated with following equations: low-side (1) high-side (2) these equations simplify under the assumption of r l = 0: low-side (3) high-side (4) the maximum energy, which is converted into heat, is limited by the thermal design of the component. out putclamp.emf high side channel gnd v bb l , r l v s i s vbb out low side channel l , r l i d out v d v s( cl ) v ds( cl ) gnd v ds( cl ) i l i l ev ds(cl) v bb v ? ds(cl) r l ---------------------------------- - ln ? 1 r l i l ? v bb v ? ds(cl) ---------------------------------- - ? ?? ?? ?? i l + l r l ------ ?? = ev bb v s(cl) ? () v s(cl) r l --------------- - ln ? 1 r l i l ? v s(cl) --------------- - ? ?? ?? ?? i l + l r l ------ ?? = e 1 2 -- - li l 2 1 v bb v bb v ? ds(cl) ---------------------------------- - ? ?? ?? ?? ? = e 1 2 -- - li l 2 1 v bb v s(cl) --------------- - ? ?? ?? ?? ? =
data sheet 18 rev. 1.0, 2010-02-18 spi driver for enhanced relay control TLE7236SE power stages 6.4 timing diagrams the power transistors are switched on and off with a dedicated slope via the inx bits of the serial peripheral interface (spi). the switching times t on and t off are designed equally. figure 6 switching a resistive load in input mode, a high signal at the input pin is equivalent to a spi on command and a low signal to spi off command respectively. please refer to section 9.3 for details on spi protocol. in v ds t switchon .emf t on t off t 20% 80%
spi driver for enhanced relay control TLE7236SE power stages data sheet 19 rev. 1.0, 2010-02-18 6.5 electrical characteristics unless otherwise specified: v dd = 3.0 v to 5.5v, v bat = 9.0 v to 16v, t j = -40 c to +150 c typical values: v dd = 5.0 v, v bat = 13.5 v, t j = 25 c pos. parameter symbol limit values unit test conditions min. typ. max. output characteristics 6.5.1 on-state resistance r ds(on) ? channel 0, 1, 4, 5, 6, 7 ? 0.85 ? i l = 220 ma t j = 25 c ?1.41.8 t j = 150 c channel 2, 3 ? 1.6 ? i l = 110 ma t j = 25 c ?2.63.8 t j = 150 c 6.5.2 nominal load current i out(nom) ma all channels on t a = 100 c t j,max = 150 c based on r thja channel 0, 1, 4, 5, 6, 7 280 410 ? 1) 1) not subject to production test, specified by design. channel 2, 3 140 205 ? 1) 6.5.3 output leakage current in sleep mode i out(sleep) ??1 a v ds = 13.5 v t j = 25 c 1) ??2 t j = 85 c 1) ??5 t j = 150 c 6.5.4 output clamping voltage v out_s(cl) ?? -16v? v out_ds(cl) 41??v? input characteristics (in & lhi) 6.5.5 l level v in(l) 0?0.6v? 6.5.6 h level v in(h) 1.8 ? 5.5 v ? 6.5.7 input voltage hysteresis ? v in ?0.1?v 1) 6.5.8 l-input pull-down current i in(l) 1.5 ? ? a v in = 0.6 v 1) 6.5.9 h-input pull-down current i in(h) 10 40 80 a v in = 5 v timings 6.5.10 turn-on time v ds = 20% v bat t on s v bb = 13.5 v resistive load channel 0, 1,4,5 ? ? 100 i ds = 250 ma channel 2, 3 ? ? 100 i ds = 120 ma channel 6,7 ? ? 100 i ds = 250 ma 6.5.11 turn-off time v ds = 80% v bb t off s v bb = 13.5 v resistive load channel 0, 1, 4, 5 ? ? 100 i ds = 250 ma channel 2, 3 (hs) ? ? 100 i ds = 120 ma channel 6, 7 (ls) ? ? 100 i ds = 250 ma
data sheet 20 rev. 1.0, 2010-02-18 spi driver for enhanced relay control TLE7236SE power stages 6.6 command description input configuration registers icr01 000 b 3210 inx1 inx0 rw rw icr23 001 b 3210 inx3 inx2 rw rw icr45 010 b 3210 inx5 inx4 rw rw icr67 011 b 3210 inx7 inx6 rw rw field bits type description inxn n = 7 to 0 [3:2], [1:0] rw input multiplexer configuration channel n 00 channel n is switched off 01 channel n is switched by input 1 10 channel n is switched by input 2 11 channel n is switched on
spi driver for enhanced relay control TLE7236SE protection functions data sheet 21 rev. 1.0, 2010-02-18 7 protection functions the device provides embedded protective functions. integrated protection functions are designed to prevent ic destruction under fault conditions described in this data sheet. fault conditions are considered as ?outside? normal operating range. protection functions are not designed for continuous repetitive operation. 7.1 over load protection the TLE7236SE is protected in case of over load or short circuit of the load. after time t off(ovl) , the over loaded channel n switches off and the according diagnosis flag dn is set. the channel can be switched on after clearing the protection latch by command cmd.cpl = 1. the cpl command clears itself with the next valid spi communication frame. please refer to figure 7 for details. figure 7 shut down at over load 7.2 over temperature protection a temperature sensor for each channel causes an overheated channel to switch off to prevent destruction. the according diagnosis flag is set. this flag is also set in off state, if the regarding channel temperature is too high.the channel can be only switched on after clearing the protection latch by spi command cmd.cpl = 1. the cpl command clears itself with the next valid spi communication frame. please refer to ?diagnostic features? on page 23 for information on diagnosis features. 7.3 esd protection there is a designed in protection against esd disturbances up to the specified limit by using the defined model. please see electrical characteristics ?esd susceptibility on all pins? on page 11 7.4 reverse polarity protection there is a reverse polarity protection implemented in the TLE7236SE. this protection has to be divided into two parts. first the protection of the control circuits and second in the protection of the power transistors. the control circuits are reverse polarity protected by protective measures in the ground connection. in case of reverse polarity, there is no current flow through the control circuits. the power transistors contain intrinsic body diodes that cause power dissipation. the reverse current through these intrinsic body diodes has to be limited by the connected loads. the over temperature and over load protection are not active during reverse polarity. 7.5 loss of v bb in case of loss of v bb connection in on-state, all inductances of the loads have to be demagnetized through the an additional path from v bb to ground. usually this path is given somewhere in the pcb circuitry, for example, as a suppressor diode like in the application diagram (see d1 in figure 14 ?application diagram? on page 35 ). in i d0 t t overload.emf t off(ov l) i d0(ovl) cpl = 1 b d0 = 1 b d0 = 00 b
data sheet 22 rev. 1.0, 2010-02-18 spi driver for enhanced relay control TLE7236SE protection functions 7.6 electrical characteristics unless otherwise specified: v dd = 3.0 v to 5.5v, v bat = 9.0 v to 16v, t j = -40 c to +150 c typical values: v dd = 5.0 v, v bat = 13.5 v, t j = 25 c pos. parameter symbol limit values unit test conditions min. typ. max. over load protection 7.6.1 over load detection current at channel 0,1,4,5,6,7 i out(ovl) 0.5 1.0 a 7.6.2 over load detection current at channel 2,3 i out(ovl) 0.22 0.5 a 7.6.3 over load shut-down delay time t off(ovl) 60 s over temperature protection 7.6.4 thermal shut down temperature t j(sc) 150 170 1) 1) not subject to production test, specified by design c
spi driver for enhanced relay control TLE7236SE diagnostic features data sheet 23 rev. 1.0, 2010-02-18 8 diagnostic features the spi of TLE7236SE provides diagnosis information about the device and about the load. the diagnosis information of the protective functions of channel n is latched in the diagnosis flags dn . it is cleared by the spi command cmd.cpl = 1. the cpl command clears itself with the next valid spi communication frame. the open load diagnosis of channel n is latched in the diagnosis flag oln . this flag is cleared by reading the according diagnosis register. following table shows possible failure modes and the according protective and diagnostic action. failure mode comment open load diagnosis, when channel n is switched on: none diagnosis, when channel n is switched off: according to voltage level at the output pin, flag oln is set after time t d(ol) . a diagnosis current can be enabled by spi command dccr.dcenn = 1. over temperature when over temperature occurs, the according diagnosis flag dn is set. if the affected channel n was active it is switched off. the diagnosis flags are latched until they have been cleared by spi command cmd.cpl = 1. over load (short circuit) when over load is detected at channel n , the affected channel is switched off after time t off(ovl) and the dedicated diagnosis flag dn is set. the diagnosis flags are latched until they have been cleared by spi command cmd.cpl = 1.
data sheet 24 rev. 1.0, 2010-02-18 spi driver for enhanced relay control TLE7236SE diagnostic features 8.1 electrical characteristics unless otherwise specified: v dd = 3.0 v to 5.5v, v bat = 9.0 v to 16v, t j = -40 c to +150 c typical values: v bat = 13.5 v, v dd = 5.0 v, t j = 25 c pos. parameter symbol limit values uni t test conditions min. typ. max. off state diagnosis 8.1.1 open load diagnosis delay time t d(ol) 100 ? 250 s? high side channels 0,1,2,3 8.1.2 open load detection threshold voltage for channel 0,1,2,3 v d(ol0..3) 345v 1) 1) open load detection voltages are referenced to ground 8.1.3 output diagnosis current channel 0,1,2,3 i l(dc0..3) 100 200 300 a measured at v d(ol) threshold configurable channels 4,5 8.1.4 open load detection threshold voltage for channel 4,5 in all configurations v d(ol4,5) 345v 1) 8.1.5 output diagnosis current channel 4,5 in high side configuration i l(dchs) 100 200 300 a measured at v d(ol) threshold 8.1.6 output diagnosis current channel 4,5 in low side configuration i l(dcls) 100 200 300 a measured at v d(ol) threshold low side channels 6,7 8.1.7 open load detection threshold voltage for channel 6,7 v d(ol6,7) 345v 1) 8.1.8 output diagnosis current channel 6,7 i l(dc6,7) 100 200 300 a measured at vol threshold on state diagnosis (see also protection in chapter 7 ) 8.1.9 over load detection current at channel 0,1,4,5,6,7 i l(ovl) 0.5? 1.0a? 8.1.10 over load detection current at channel 2,3 i l(ovl) 0.22 ? 0.5 a ? 8.1.11 over load detection delay time at all channels t off(ovl) ??60 s?
spi driver for enhanced relay control TLE7236SE diagnostic features data sheet 25 rev. 1.0, 2010-02-18 8.2 command description diagnosis registers (read only, register bank rb = 1) r/ dr01 00 b 3210 ol1 d1 ol0 d0 rrrr dr23 01 b 3210 ol3 d3 ol2 d2 rrrr dr45 10 b 3210 ol5 d5 ol4 d4 rrrr dr67 11 b 3210 ol7 d7 ol6 d6 rrrr field bits type description dn n = 7 to 0 2, 0 r diagnostic feedback of channel n 0 normal operation 1 over load or over temperature switch off occurred oln n = 7 to 0 3, 1 r open load detection of channel n 0 normal operation 1 open load at off-state occurred cmd command register 110 b 3210 wake stb rst cpl r/w r/w r/w r/w field bits type description cpl 0 r/w please refer to section 7 for description rst 1 r/w please refer to section 5.3 for description stb 2 r/w please refer to section 5 for description wake 3 r/w please refer to section 5 for description
data sheet 26 rev. 1.0, 2010-02-18 spi driver for enhanced relay control TLE7236SE diagnostic features diagnosis current configuration register dccr0 100 b 3210 dcen3 dcen2 dcen1 dcen0 r/w r/w r/w r/w dccr1 101 b 3210 dcen7 dcen6 dcen5 dcen5 r/w r/w r/w r/w field bits type description dcenn n = 7 to 0 3 to 0 r/w diagnosis current enable channel n 0 diagnosis current disabled 1 diagnosis current enabled
spi driver for enhanced relay control TLE7236SE serial peripheral interface (spi) data sheet 27 rev. 1.0, 2010-02-18 9 serial peripheral interface (spi) the diagnosis and control interface is based on a serial peripheral interface (spi). the spi is a full duplex synchronous serial slave interface, which uses four lines: so, si, sclk and cs . data is transferred by the lines si and so at the data rate given by sclk. the falling edge of cs indicates the beginning of a data access. data is sampled in on line si at the falling edge of sclk and shifted out on line so at the rising edge of sclk. each access must be terminated by a rising edge of cs . a modulo 8 counter ensures that data is taken only, when a multiple of 8 bit has been transferred. the interface provides daisy chain capability. figure 8 serial peripheral interface the spi protocol is described in section 9.3 . it is reset to the default values after reset. 9.1 spi signal description cs - chip select: the system micro controller selects the TLE7236SE by means of the cs pin. whenever the pin is in low state, data transfer can take place. when cs is in high state, any signals at the sclk and si pins are ignored and so is forced into a high impedance state. cs high to low transition: ? the diagnosis information is transferred into the shift register. ? so changes from high impedance state to high or low state depending on the logic or combination between the transmission error flag ( ter ) and the signal level at pin si. as a result, even in daisy chain configuration, a high signal indicates a faulty transmission. for details, please refer to figure 9 . this information stays available to the first rising edge of sclk. figure 9 transmission error flag on so line lsb 6 5 4 3 2 1 lsb 6 5 4 3 2 1 cs msb msb so si cs sclk time spi.emf te r. em f si spi or ter 0 1 so cs sclk s so s si
data sheet 28 rev. 1.0, 2010-02-18 spi driver for enhanced relay control TLE7236SE serial peripheral interface (spi) cs low to high transition: ? command decoding is only done, when after the falling edge of cs exactly a multiple (1, 2, 3, ?) of eight sclk signals have been detected. in case of faulty transmission, the transmission error flag ( ter ) is set and the command is ignored. ? data from shift register is transferred into the input matrix register. sclk - serial clock: this input pin clocks the internal shift register. the serial input (si) transfers data into the shift register on the falling edge of sclk while the serial output (so) shifts diagnostic information out on the rising edge of the serial clock. it is essential that the sclk pin is in low state whenever chip select cs makes any transition. si - serial input: serial input data bits are shifted in at this pin, the most significant bit first. si information is read on the falling edge of sclk. the 8 bit input data consist of two parts (control and data). please refer to section 9.3 for further information. so serial output: data is shifted out serially at this pin, the most significant bit first. so is in high impedance state until the cs pin goes to low state. new data will appear at the so pin following the rising edge of sclk. please refer to section 9.3 for further information. 9.2 daisy chain capability the spi of TLE7236SE provides daisy chain capability. in this configuration several devices are activated by the same cs signal mcs . the si line of one device is connected with the so line of another device (see figure 10 ), which builds a chain. the ends of the chain are connected with the output and input of the master device, mo and mi respectively. the master device provides the master clock mclk, which is connected to the sclk line of each device in the chain. figure 10 daisy chain configuration in the spi block of each device, there is one shift register where one bit from si line is shifted in each sclk. the bit shifted out can be seen at so. after 8 sclk cycles, the data transfer for one device has been finished. in single chip configuration, the cs line must go high to make the device accept the transferred data. in daisy chain configuration the data shifted out at device #1 has been shifted in to device #2. when using three devices in daisy chain, three times 8 bits have to be shifted through the devices. after that, the mcs line must go high (see figure 11 ). si device 1 spi sclk so cs si device 2 spi sclk so cs si device 3 spi sclk so cs mo mi mcs mclk spi _dasychain.emf
spi driver for enhanced relay control TLE7236SE serial peripheral interface (spi) data sheet 29 rev. 1.0, 2010-02-18 figure 11 data transfer in daisy chain configuration 9.3 spi protocol the control and diagnosis function of the TLE7236SE is based on two register banks which are accessed via following spi protocol. the control register bank contains eight registers (with 4 bit each) addressed by a 3 bit pointer. the diagnosis register bank contains four registers (with 4 bit each) addressed by a 2 bit pointer. an additional indication bit is available to differentiate between standard diagnosis information and data read from a register bank. control and diagnosis mode note: reading a register needs two spi frames. in the first frame the rd command is sent. in the second frame, the output at spi signal so will contain the requested information. any command can be executed in the second frame. cs 1) 1) this bit is valid between cs hi -> lo and first sclk lo -> hi transition. 76543210 write register command si 1 addr data read register command si 0 addr x x 0 rb read standard diagnosis si 0xxxxx1x standard diagnosis s o ter 0 awk lh d67 d45 d23 d01 second frame of read command s o ter 0 1 addr (diagnosis) data s o ter 1 addr (control) data mi mo mcs mclk s i devi ce 3 si device 2 si device 1 s o devi ce 3 so device 2 s o devi ce 1 time spi _dasychain2. emf
data sheet 30 rev. 1.0, 2010-02-18 spi driver for enhanced relay control TLE7236SE serial peripheral interface (spi) standard diagnosis: 9.4 register overview field bits type description ter transmission error 0 previous transmission was successful (modulo 8 clocks received) 1 previous transmission failed or first transmission after reset rb 0 register bank 0 contr control register bank 1 diag diagnosis register bank (read only) addr 6:4 address pointer to register for read and write command data 3:0 data data written to or read from register selected by address addr field bits type description awk 5 awake, device active lh 4 limp home mode active dxy 3, 2, 1, 0 failure mode alert of channel x and y (overtemp, overload) ol ? common open load flag for all channels control register bank name addr3210default 1) 1) the default values are set after v bb power-on, stb-command and rst-command all command bits are cleared at the end of transmission, respectively after execution type icr01 000 b inx1 inx0 0 h r/w icr23 001 b inx3 inx2 0 h r/w icr45 010 b inx5 inx4 0 h r/w icr67 011 b inx7 inx6 0 h r/w dccr0 100 b dcen3 dcen2 dcen1 dcen0 0 h r/w dccr1 101 b dcen7 dcen6 dcen5 dcen4 0 h r/w cmd 110 b wake stb rst cpl 2) 2) cpl bit needs a valid next spi communication frame to be cleared 0 h w unused 111 b ????0 h ? input word (see chapter 6.6 for detailed description) name state 1 0 inx0 - inx7 off 0 0 in1 0 1 in2 or in3 1 0 on 1 1
spi driver for enhanced relay control TLE7236SE serial peripheral interface (spi) data sheet 31 rev. 1.0, 2010-02-18 9.5 timing diagrams figure 12 timing diagram diagnosis register bank (read only) name addr3210 dr01 000 b ol1 d1 ol0 d0 dr23 001 b ol3 d3 ol2 d2 dr45 010 b ol5 d5 ol4 d4 dr67 011 b ol7 d7 ol6 d6 cs sclk si t cs(lead) t cs( td ) t cs(lag) t scl k( h) t scl k( l) t scl k( p) t si( su ) t si( h ) so t so( v) t so(en) t so( dis) 0.7 v cc 0.2 v cc 0.7 v cc 0.2 v cc 0.7 v cc 0.2 v cc 0.7 v cc 0.2 v cc spi timing.emf
data sheet 32 rev. 1.0, 2010-02-18 spi driver for enhanced relay control TLE7236SE serial peripheral interface (spi) 9.6 electrical characteristics unless otherwise specified: v dd = 3.0 v to 5.5v, v bat = 9.0 v to 16v, t j = -40 c to +150 c typical values: v dd = 5.0 v, v bat = 13.5 v, t j = 25 c pos. parameter symbol limit values unit test conditions min. typ. max. input characteristics (cs , sclk, si) 9.6.1 l level of pin cs sclk si v cs(l) v sclk(l) v si(l) 0?0.2* v dd v? 9.6.2 h level of pin cs sclk si v cs(h) v sclk(h) v si(h) 0.5* v dd ? v dd v? 9.6.3 l-input pull-up current through cs i cs(l) 54090 a v cs = 0 v v dd = 5 v 9.6.4 h-input pull-up current through cs i cs(h) 2.5 ? ? a 1) v dd = 5 v v cs = 0.5* v dd 9.6.5 l-input pull-down current through pin sclk si i sclk(l) i si(l) 1.5 ? ? a 1) v dd = 5 v v sclk = v si = 0.2* v dd 9.6.6 h-input pull-down current through pin sclk si i sclk(h) i si(h) 10 40 80 a 1) v dd = 5 v v sclk = v si = v dd output characteristics (so) 9.6.7 l level output voltage v so(l) 0?0.4v i so = +2 ma 9.6.8 h level output voltage v so(h) v dd - 0.4 v ? v dd i so = -1.5 ma 9.6.9 output tristate leakage current i so(off) -10 ? 10 a v cs = v dd timings 9.6.10 serial clock frequency f sclk 0?5mhz? 9.6.11 serial clock period t sclk(p) 200 ? ? ns ? 9.6.12 serial clock high time t sclk(h) 50 ? ? ns 1) 9.6.13 serial clock low time t sclk(l) 50 ? ? ns 1) 9.6.14 enable lead time (falling cs to rising sclk) t cs(lead) 250 ? ? ns 1) 9.6.15 enable lag time (falling sclk to rising cs ) t cs(lag) 250 ? ? ns 1) 9.6.16 transfer delay time (rising cs to falling cs ) t cs(td) 250 ? ? ns 1) 9.6.17 data setup time (required time si to falling sclk) t si(su) 20 ? ? ns 1) 9.6.18 data hold time (falling sclk to si) t si(h) 20 ? ? ns 1)
spi driver for enhanced relay control TLE7236SE serial peripheral interface (spi) data sheet 33 rev. 1.0, 2010-02-18 9.6.19 output enable time (falling cs to so valid) t so(en) ??200ns c l = 20 pf 1) 9.6.20 output disable time (rising cs to so tri-state) t so(dis) ??200ns c l = 20 pf 1) 9.6.21 output data valid time with capacitive load t so(v) ??100ns c l = 20 pf 1) 1) not subject to production test, specified by design. unless otherwise specified: v dd = 3.0 v to 5.5v, v bat = 9.0 v to 16v, t j = -40 c to +150 c typical values: v dd = 5.0 v, v bat = 13.5 v, t j = 25 c pos. parameter symbol limit values unit test conditions min. typ. max.
data sheet 34 rev. 1.0, 2010-02-18 spi driver for enhanced relay control TLE7236SE package outlines 10 package outlines figure 13 pg - dso20-45 (plastic green dual small outline package) green product (rohs compliant) to meet the world-wide customer requirements for environmentally friendly products and to be compliant with government regulations the device is available as a green product. green products are rohs-compliant (i.e pb- free finish on leads and suitable for pb-free soldering according to ipc/jedec j-std-020). gps05094 1.27 0.2 20x 9 x 1.27 = 11.43 0.35 +0.15 2) 0.2 -0.1 0.05 12.8 1) -0.2 110 11 20 8? 8? seating plane 1.1 stand off 2.65 max. 2.45 20x 0.1 -0.2 0.2 -0.1 ejector mark depth 0.2 max. index marking 1) does not include plastic or metal protrusion of 0.15 max. per side 2) does not include dambar protrusion per side 0.35 x 45? 8? -0.2 1) 7.6 8? 8? max. ?.3 10.3 0.4 +0.8 0.23 +0.09 for further information on alternative packages, please visit our website: http://www.infineon.com/packages . dimensions in mm
spi driver for enhanced relay control TLE7236SE application information data sheet 35 rev. 1.0, 2010-02-18 11 application information note: the following information is given as a hint for the implementation of the device only and shall not be regarded as a description or warranty of a certain functionality, condition or quality of the device. figure 14 shows a simplified application circuit. vdd need to be externally reverse polarity protected. figure 14 application diagram note: this is a very simplified example of an application circuit. the function must be verified in the real application. the circuit above shows a example of using this device in a automotive target application. d1 is optional for loss of battery or loss of ground if no other circuit on this battery feed can limit the voltage to the max. rating of the device (-40 v) . c2 is for emc and to stabilize the digital driver, recommended value is 47nf. there are no resistors to the c needed due to the internal reverse polarity protection. for further information you may contact http://www.infineon.com/spider so sclk si cs gnd vdd application _lg.emf out0 out1 out6 out7 lowside loads spi uc pwm v dd c2 vbb highside loads out2 out3 d4 s4 d5 s5 pwm lho in2 in1 lh i vbat d1
data sheet 36 rev. 1.0, 2010-02-18 spi driver for enhanced relay control TLE7236SE revision history 12 revision history revision date changes rev. 1.0 2010-02-18 datasheet released
edition 2010-02-18 published by infineon technologies ag 81726 munich, germany ? 2008 infineon technologies ag all rights reserved. legal disclaimer the information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. with respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, infineon technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party. information for further information on technology, delivery terms and conditions and prices, please contact the nearest infineon technologies office ( www.infineon.com ). warnings due to technical requirements, components may contain dangerous substances. for information on the types in question, please contact the nearest infineon technologies office. infineon technologies components may be used in life-support devices or systems only with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered.

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